Location:
Search - RISC CPU
Search list
Description: 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
Platform: |
Size: 361472 |
Author: QINZ |
Hits:
Description: 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
Platform: |
Size: 111616 |
Author: YK97 |
Hits:
Description: wb_switch，opencore，精简指令cpu设计-wb_switch，opencore，risc cpu design。
Platform: |
Size: 2048 |
Author: 浮萍 |
Hits:
Description: 精简指令cpu设计，外扩电路设计，led开发板驱动-wb_sw_leds，opencore，risc cpu design。
Platform: |
Size: 1024 |
Author: 浮萍 |
Hits:
Description: 七段数码管驱动电路，fpga，seg7，altera开发板例子-risc-cpu design，seg7，fpga
Platform: |
Size: 2048 |
Author: 浮萍 |
Hits:
Description: 可综合的verilog描述的精简指令集的cpu设计-Verilog description integrated RISC CPU design
Platform: |
Size: 394240 |
Author: david |
Hits:
Description: SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
Platform: |
Size: 47104 |
Author: lvpw |
Hits:
Description: 本例子是一个精简指令集CPU，非常好用经过测试-This example is a RISC CPU, very handy tested
Platform: |
Size: 1770496 |
Author: apang |
Hits:
Description: 13.2 RISC-CPU设计
13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
Platform: |
Size: 445440 |
Author: shixiaodong |
Hits:
Description: RIsc 处理区 内附仿真文件和相关报告-RIsc treatment area containing a simulation files and related reports
Platform: |
Size: 431104 |
Author: rocky |
Hits:
Description: 精简指令集CPU，可完成移位，跳转等简单功能，适用于FPGA学习，本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
Platform: |
Size: 1884160 |
Author: 晓东 |
Hits:
Description: 经典RISC CPU 设计，和PCI8位指令单片机兼容，值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
Platform: |
Size: 1090560 |
Author: HUAJUN |
Hits:
Description: The Texas Instruments CC430 family of ultralow-power microcontroller system-on-chip (SoC) with integrated RF
transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of
applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life
in portable measurement applications. The device features the powerful MSP430 16-bit RISC CPU, 16-bit
registers, and constant generators that contribute to maximum code efficiency.
Platform: |
Size: 1563648 |
Author: dmimed |
Hits:
Description: DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
Platform: |
Size: 3072 |
Author: 石建刚 |
Hits:
Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: |
Size: 822272 |
Author: wang |
Hits:
Description: 超低功耗微控制器德州仪器MSP430FR698x和MSP430FR598x家庭由多个设备具有不同的套外设。该体系结构，结合7种低功耗模式被优化以实现延长的电池寿命，例如在流量计量应用。该器件具有一个强大的16位RISC CPU，16位寄存器和有助于获得最大编码效率的常数发生器。-Ultra-low-power microcontroller family Texas Instruments MSP430FR698x and MSP430FR598x multiple devices with different sets of peripherals. The architecture, combined with 7 kinds of low-power mode is optimized to achieve extended battery life, for example, in flow measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers and help get the maximum coding efficiency constant generator.
Platform: |
Size: 25719808 |
Author: 侯波 |
Hits:
Description: systemC模仿RISC CPU的简单功能-system C foumulate the simple function of RISC CPU
Platform: |
Size: 6035456 |
Author: 安延文 |
Hits:
Description: systemC模仿RISC CPU的一般功能-systemC imitate RISC CPU' s general functions
Platform: |
Size: 6130688 |
Author: 安延文 |
Hits:
Description: systemC模仿RISC CPU的完全功能，包括时序，信号-systemC imitate fully functional RISC CPU, including the timing, signal
Platform: |
Size: 5943296 |
Author: 安延文 |
Hits:
Description: 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
Platform: |
Size: 520192 |
Author: ljt |
Hits: